Circuit board test systems are used to test large numbers of printed circuit boards by verifying electrical functionality and continuity between various test points on the circuit board. Continuity and lack of continuity are generally detected through the use of test fixtures having an array of test probes for making electrical contact with individual test points on the printed circuit board. Test systems vary in their approach to bringing the array of test probes into contact with test points on the circuit board. One test system for testing loaded circuit boards includes spring biased test probes mounted on a probe plate, and a bellows or vacuum-actuated means of applying pressure between the spring probes and the circuit board test points. The test system also includes a test analyzer which generally includes a computer-controlled detection system for applying selected electrical signals to selected contacts to sense continuity and provide test results. An example of a prior art test system is described in U.S. Pat. No. 4,138,186 to Long, et al.
Loaded printed circuit boards are usually crowded with various electrical components, including arrays of integrated circuit packages. These packages typically include integrated circuits packaged in an insulated housing with a plurality of thin, parallel electrical leads extending from the housing. The leads from the integrated circuit package can be bent into various configurations which makes testing of the packages difficult. For instance, integrated circuit packages with J-lead or gull-wing lead configurations are common. It is common to mount large numbers of these integrated circuit packages close to one another on the circuit board to save board space. If a number of integrated circuit packages are crowded together on a loaded circuit board, there is usually little room left around the integrated circuit packages for making electrical contact between spring probes on a test unit and the leads on the circuit packages or other circuit elements adjacent to the packages.
Semiconductor chips are often produced in dual in-line packages having two sets of spaced apart leads extending along opposite sides of the package. In testing dual in-line packages, the package is commonly plugged into a test head so that the leads on the integrated circuit package engage the test head contacts to perform a series of tests, after which the circuit package is removed from the test head. Test heads for such integrated circuit packages are described in U.S. Pat. Nos. 3,701,077 to Kelly, Jr., and 3,573,617 to Randolph, et al. In most instances, these test heads are used for testing dual in-line packages before they are mounted on printed circuit boards. It is difficult to test dual in-line packages and other integrated circuit packages after they are mounted on a loaded circuit board, especially when the packages are crowded together on the board. Loaded circuit boards are normally tested with the test units described above, in which the spring probes are arranged to make electrical contact with the various test points on the board. In order for the test unit to make electrical contact with rows of leads on integrated circuit packages, it has been proposed to mount integrated circuit test heads, or test sockets, on the probe plate of the test fixture. When the probe plate and printed circuit board are drawn together in the test unit, the test socket passes around the perimeter of the integrated circuit package for making electrical contact with the leads on the package. However, several problems arise from this arrangement:
(a) If the packages are not accurately aligned with the test sockets, the test sockets may not fit around the integrated circuit package. PA1 (b) It is necessary to make special cut-outs in the probe plate for mounting the test sockets. PA1 (C) With the cut-outs in the probe plate, it is difficult to mount spring probes closely adjacent to the cut-out for contacting components closely adjacent to the integrated circuit packages. PA1 (d) Relatively high pressure is required to force the test socket contacts into electrical contact with the leads on the integrated circuit package.
In addition to dual in-line packages, many integrated circuit packages are now available using surface-mount packaging technology which packs electronic functions more densely on circuit boards. This dense packing enables manufacturers to produce smaller boards at lower cost or to provide more functions at the same cost when compared with dual in-line packaging techniques. One common form of surface-mount packaging is the so-called plastic leaded chip-carrier (PLCC) package. Generally speaking, PLCC packages house memory and microprocessor integrated circuit chips requiring large numbers of leads spaced apart along all four sides or at least two opposite sides of a square shaped housing. Because of their small size and large number of leads, it is difficult to test multiple arrays of closely spaced apart PLCC devices mounted on loaded printed circuit boards. The configuration of the leads also makes it difficult to test PLCC devices. In some integrated circuit packages, the lead configuration prevents any contact being made between the leads and the test probes of a test unit. For instance, in packages with leads in a gull-wing configuration, the solder joints are sensitive to external pressures and therefore contact with test probes should be avoided to prevent fracturing the solder joints.
Thus, there is a need to provide a means for testing loaded printed circuit boards having large numbers of integrated circuit packages mounted close to one another on the board. The need for such a test system is especially critical because of the expanding use of surface-mount packages such as PLCC devices which are particularly difficult to test. PLCC devices in particular can be difficult to test with a conventional test head because the PLCC packages can easily become skewed from a square position relative to the circuit board, or because of the need to avoid pressure contact between the leads and the test unit. There is also a need for a test system that does not cause undue delays during testing and is adaptable readily to testing circuit boards having multiple integrated circuit packages mounted in various patterns on different boards.